AI Chip Architectures and Accelerators
· NPUs, TPUs, and reconfigurable AI accelerators
· In-memory and near-memory computing architectures
· Sparse neural network accelerators and pruning-aware hardware
· Heterogeneous platforms integrating CPU, GPU, NPU, and FPGA

Advanced Semiconductor Devices and Process Technologies
· Sub-3nm logic devices: GAA-FETs, CFETs, and 2D material transistors
· Advanced lithography (EUV, high-NA EUV) and patterning techniques
· Novel interconnects and backside power delivery networks
· Monolithic 3D integration and chiplets for heterogeneous integration

Memory Technologies and Storage for AI Systems
· Emerging non-volatile memories (MRAM, ReRAM, PCM) and logic integration
· HBM, processing-in-memory (PIM), and memory-centric architectures
· 3D NAND, storage-class memory, and AI-optimized storage hierarchies
· Cache design, memory consistency, and data placement for AI workloads

Design Automation, EDA, and AI-Driven IC Design
· AI/ML-assisted EDA for logic synthesis, placement, and routing
· RL-driven chip floorplanning and physical design optimization
· Automated design space exploration and RTL-to-GDSII generation
· AI-driven yield prediction, defect detection, and reliability optimization

System-Level Integration and Software-Hardware Co-Design
· Chiplet-based SiP and advanced packaging (2.5D/3D)
· Compiler and runtime optimization for AI accelerators
· Hardware-aware NAS and model compression
· Scalable training/inference systems for large language models (LLMs)

Emerging Paradigms, Reliability, and Security
· Neuromorphic computing and spiking neural network (SNN) hardware
· Quantum, optical, and analog AI accelerators
· Hardware security: side-channel attacks, anti-counterfeiting, and trust anchors
· Reliability: aging, thermal management, and fault-tolerant design